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Why is Design Constraints (SDC) Validation Critical at RTL?

March 12th, 2019 10 AM PT

Static and formal verification techniques help implement the shift-left strategy for verification closure. While this strategy is commonly used in functional verification and clock domain crossing (CDC) analysis, validation of the Synopsys Design Constraints (SDC), which is a very important aspect of the design flow, is ignored at early stages. Clean design constraints are required for accurate CDC analysis as well as RTL synthesis. Wrong timing exceptions like false paths and multi-cycle paths also result in functional bugs and silicon re-spins. Typically, SDC validation is done late at the netlist level, which results in design iterations and missed bugs. In this webinar, we will talk about why constraint validation is important at RTL, highlight the different problems, and how designers can solve these problems early in the flow.

Tanveer Singh
Applications Engineer, Sr Staff

Tanveer Singh is a Senior Application Engineer working on, Constraints verification, Exception verification, Clock Domain crossing and Lint technologies and has been with Synopsys since 2005. He is driving next generation tools and flows in several areas like constraints validation, Advanced CDC verification, exception verification, hybrid verification flows for static verification as well as working on defining next level features in current synopsys tools in the Static Verification domain. Prior to Synopsys he was working with Texas Instruments where he was leading the Netlist simulation flow and verification.
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