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UPF Signoff Using Design Independent Checker

March 6th, 2019 10 AM PT

With increasing SoC complexity, growing design sizes and advanced power-aware architectures, early and efficient static low power verification is essential to reduce turnaround times and enable faster time to market.

UPF and design development goes hand in hand, but schedules may vary. It is difficult to verify the accuracy and correctness of the UPF (both semantically and syntactically) without the design being available. There are many UPF issues which can be caught independent of the design with the new design independent UPF checker. This webinar will showcase the latest capabilities for UPF sign-off using the VC UPF methodology.

Himanshu Bhatt
Senior Staff Applications Engineer
Susantha Wijesekara
Sr. Applications Engineer

Himanshu Bhatt is a Senior Staff Applications Engineer with the low power verification team in the verification group at Synopsys Inc. He has 18+ years of overall experience spanning EDA (Electronic Design Automation) and Semiconductor industry including ASIC design and verification using various verification methodologies like eRM, UVM, CPF, UPF, formal, equivalence checking. He is currently working as a Low Power Verification Specialist to help designers define and refine their low power verification flow.

Susantha Wijeskara is a Senior Applications Engineer II for the low power verification team in the verification group at Synopsys. He has 6+ years of experience, starting his career as a verification engineer on low power verification products in the SpyGlass platform from Atrenta. He currently works as a Low Power Verification Application Engineer for Synopsys’ VC LP product by supporting VC LP customers.

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