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Addressing Exascale Emulation Debug Complexity – The case for a system-level approach

February 27th, 2019 10 AM PT

Emulation is established as mainstream validation platform leading to successful tape out and silicon. Due to performance and capacity advantages, it allows validation of billion gate design running billion cycle applications. To debug an issue in such a system, poses several challenges due to amount of debug data generated. Traditional iterative waveform level debug is no longer effective as the sole means to find root causes for incorrect behavior. Even a million cycle capture is a small fraction of the total test length and multiple iterations are required to find the window of interest. In case of transient failures of the emulation setup, such methods can easily run in circles and finding the failure is becoming unpredictable.

In this webinar, we present how to use ZeBu to cut debug time after a failure has been reported during a multi-billion cycles regression. Through unlimited streaming of the design’s system log all key information is captured during the emulation run. From there the user can quickly determine the window of interest and using the proven ZeBu replay technology and powerful Verdi debug, the bug can be root caused quickly.

Ribhu Mittal
Director, Program Management

Ribhu Mittal is a seasoned emulation professional with 18+ years of domain expertise spawning solutions from all major vendors. Ribhu holds a master’s degree in Electrical and Computer engineering and presently works with Synopsys in Director role focusing on Emulation applications and customer use models.
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