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An Efficient Hierarchical Verification Flow for Low Power Designs

February 21st, 2019 10 AM PT

Growing design sizes, low power complexity, and the need for early stage verification is forcing designers to adopt hierarchical verification flows. Traditionally for hierarchical verification, designers use black box flow, liberty based hierarchical flow, ETM flow, or stub/glass box flows that have various trade-offs for accuracy of results and performance. While black box flow is best for performance, the full flat runs produces the best quality results since the full design is available for checks.

Adopting a new flow called SAM (Static Abstract Model) for hierarchical verification can provide guaranteed QoR by retaining enough logic needed for hierarchical modules while the performance of the runs would be much better than flat runs. Additionally, this flow enables the top-level integrator to focus on top-level violations only; integration related issues need not worry about violations deep inside hierarchical blocks since the block owners would sign-off their blocks after review of the violations. In this webinar, we will cover the benefits of SAM flow, such as the 8X-15X runtime performance gain and reduced memory consumption compared to the full flat verification, all while not losing any QoR and greatly reducing TAT during low power verification sign-off.

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Susantha Wijesekara
Sr. Applications Engineer II
Synopsys
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Nishant Patel
Sr. Applications Engineer II
Synopsys
Susantha Wijeskara is a Senior Applications Engineer II for the low power verification team in the verification group at Synopsys. He has 6+ years of experience, starting his career as a verification engineer on low power verification products in the SpyGlass platform from Atrenta. He currently works as a Low Power Verification Application Engineer for Synopsys’ VC LP product by supporting VC LP customers.

Nishant Patel is a Senior Applications Engineer II for the low power verification team in the verification group at Synopsys. Patel has 8+ years’ experience spanning the EDA and semiconductor industry including ASIC design and verification experience using various verification methodologies like CPF, UPF, and equivalence checking. He has worked as an SoC power architect and completed end-to-end power signoff for two chips during his designing carrier. He is currently working as a Low Power Verification Specialist and driving VC LP growth in the North America region.

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