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Designing SoCs in 22ULP & 22ULL for Optimized Performance, Power & Area


Tue, Mar 5, 2019 10:00 AM PST{LOCAL_TZ}

The 22-nanometer (nm) ULP & 22ULL processes are now available from leading foundries to provide PPA (Power, Performance and Area) enhancements to 28nm processes.

Synopsys Foundation IP is designed to extend the PPA of these 22nm processes and enable SoC designers further to create a competitive advantage. 

With the combination of these 22-nm processes and the right foundation IP, designers can develop optimized SoCs for applications from set-top box, DTV, home appliances, low to mid-end mobile, Bluetooth, WiFi and other consumer/industrial products.

In this webinar, you will learn:
  • When to use the 22ULL or 22ULP processes
  • How to take advantage of the process when transitioning from other process technologies
  • How optimized embedded memories and logic libraries can enable you to minimize area and power of your SoC while achieving target performance
  • The innovative power management techniques embedded within the memories and multiple logic libraries enable you to deliver lowest total power
Ken Brock
Product Marketing Manager, Logic Libraries
Rahul Thukral
Product Marketing Manager, Embedded Memories

Ken Brock is the Product Marketing Manager for Logic Libraries at Synopsys. He works with advanced node SoC design teams and leading foundries to provide physical IP solutions for optimal performance, power, area and yield. Mr. Brock has served in the IP and EDA industries for over twenty-five years in technical, marketing, management, professional service, and product development at Virage Logic, Silvaco, Virtual Silicon, Collett International, Compass Design Automation, Mentor Graphics, and Silicon Compilers. He holds a BSEE and MBA from Fairleigh Dickinson University.

Rahul Thukral brings more than two decades of semiconductor experience to his role as Product Marketing Manager for Embedded Memories at Synopsys. Rahul has held positions ranging from engineering to field applications at Mentor Graphics and Virage Logic prior to joining Synopsys. Rahul graduated from Rutgers University with his masters in Electrical Engineering.
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