Prevent Low Power Bugs Escaping to Silicon with VC LP for Debug

Date: November 28, 2018 Time: 10:00 AM PST

Next-generation SoCs with advanced graphics, computing, machine learning and artificial intelligence capabilities are posing new unforeseen challenges in low power verification. With greater low power complexity comes bigger debug challenges. Different users have different needs and there is no “one solution fits all” methodology or technique. This webinar shares techniques for efficient low power debug for simulation, synthesis and prototyping using Synopsys VC LP.  Good debugging techniques enable design teams to “shift left” and ensure that subtle bugs do not escape to silicon.

Nishant Patel
Sr. Applications Engineer II
Tushar Parikh
Sr. Staff Engineer

Nishant Patel is a Senior Applications Engineer II for the Low Power Verification team in the verification group at Synopsys. Patel has 8+ years’ experience spanning the EDA and semiconductor industry including ASIC design and verification experience using various verification methodologies like CPF, UPF, and equivalence checking. He has worked as an SoC power architect and completed end-to-end power signoff for two chips during his designing carrier. He is currently working as a Low Power Verification Specialist and driving VC LP growth in the North America region.

Tushar Parikh is a Senior Staff Engineer in the verification group at Synopsys. He has been with Synopsys for 15 years. Parikh joined Synopsys after 5 years at Sun Microsystems. He has served as the Product Line Lead (PLL) for VC Formal and Low Power Verification. As the Low Power Verification PLL, Parikh has focused on UPF and Low Power technologies across the verification space. He has 10+ years of experience in Low Power methodology for verification and implementation and has worked with various Synopsys customers implementing low power flows for ASIC design.
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