High Speed Ethernet PHY IP Design Methodology Optimization using Custom Compiler

November 20th, 2018 10:00 AM PST

This webinar describes how the Synopsys Mixed-Signal IP team optimized their design methodology in a single custom design platform to meet the circuit design, simulations, layout and physical verification requirements of their DesignWare 56G Ethernet PHY IP.

PHY designers are constantly working towards higher performance designs to meet the insatiable need for more network bandwidth. New process technologies enable designers to deliver more performance, but at the cost of significantly more design effort. Challenges introduced by the latest process nodes include the divergence between pre-layout and post-layout simulations, high interconnect parasitics, and the need to design for reliability. We will highlight our high-speed Ethernet PHY IP design project’s key findings to show how designers can optimize their design methodology to handle these challenges while meeting aggressive schedules. 

Attendees will gain insights on:
  • The need for high-speed PHY technology for 400G and beyond Ethernet applications
  • Design considerations and methodology flows required for high-speed Ethernet SoC design
  • Leveraging Synopsys Custom Design Platform to meet PPA and schedule targets
Michael Lynch
Senior R&D Manager

Michael Lynch is a Senior R&D Manager at Synopsys in Mississauga, Ontario where he has worked on high-speed SerDes design since 2003.  He currently leads engineering teams developing Synopsys’ DesignWare® Multi-Protocol PHY IP for 32G/50G/100G applications.  His interests include the design of power efficient multi-GHz circuits in the latest nanometer CMOS FinFET processes.  He received his B.A.Sc. and M.A.Sc. degrees in electrical engineering from the University of Waterloo and University of Calgary in 2000 and 2003 respectively.
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