This website uses cookies

Cookies are small text files that can be used by websites to make a user's experience more secure and to analyze traffic to the site. We use cookies for the following purposes:

- Necessary: Cookies are required to access secure areas of the website and to provide important platform notifications. The site cannot function properly without these cookies
- Statistics: Cookies are used to track device information anonymously to better understand how visitors interact with the website.

This notice applies to the following domains:

Bottlenecks Be Gone - Automated Performance Verification with Synopsys VC VIP AutoPerformance and Verdi

Date: February 21, 2018 Time: 10:00 AM PST

Performance is a critical source of competitive advantage for modern SoCs, and performance targets need to be verified on top of functionality. SoCs can be configured in a multitude of ways with different IP and interconnect topologies, number of masters and slaves, bus widths, packet sizes, clock speeds, etc., and performance verification can quickly get overwhelming. Further, given SoC performance verification is often done towards the end of the project cycle, there is a pressing need for push-button performance verification, analysis and debug.

In this Synopsys webinar, we will outline an automated flow to perform end-to-end performance verification using Synopsys VC VIP AutoPerformance, Verdi Performance Analyzer and Verdi Protocol Analyzer. We will also include a demo of this flow using a real-world design and Synopsys VIP for Arm® AMBA® protocol.

Specifically, you will learn:

  • How to quickly create a test profile for VC VIP AutoPerformance to auto-generate stimulus for performance testing
  • How to easily preset thresholds for key metrics such as latency, bandwidth etc. to auto-detect performance bottlenecks
  • How to analyze and seamlessly debug performance issues right down to the violating transaction
Vaishnav Gorur
Product Marketing Manager
Verification Group, Synopsys

Vaishnav Gorur is currently Staff Product Marketing Manager for Debug & SoC Verification Automation products in the Verification Group at Synopsys. He has over 12 years of experience in the semiconductor and EDA industry, with roles spanning IC Design, field applications, technical sales and marketing. Prior to joining Synopsys, Vaishnav worked at Silicon Graphics, MIPS Technologies and Real Intent. He has a Masters degree in Computer Engineering from University of Wisconsin, Madison and an M.B.A. from University of California, Berkeley.

Satyapriya Acharya
Senior Manager – Applications Engineering
Verification Group, Synopsys

Satyapriya Acharya is a Senior AE Manager at Synopsys, where he manages the use of Synopsys Verification IP for ARM AMBA protocols with several key customers. He has been involved in the development, verification, and deployment of Synopsys Verification IP for the AMBA 3, AMBA 4 and AMBA 5 specifications. He has over 15 years of experience in design and verification.
close log in form button
Log In Now Not Registered?

close register form button
Register Now Already Registered?