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Top Next-Gen PCIe Verification Challenges: Equalization, RX Margining, and Retimer

Date: February 1, 2018 Time: 10:00 AM PST

Leading edge design teams are starting to evaluate and consider the adoption of PCIe Gen4 and Gen 5 specifications. While providing up to 32 GT/s on a familiar bus, adoption is not without its verification challenges. This webinar will give a brief overview of the latest PCIe specifications and address the top verification issues encountered by early adopters. We will analyze how best to overcome challenges as they relate to Retimers, Equalization, and RX Margining.
Paul Graykowski
Senior Manager Application Engineering for PCIe VIP,

Paul has been working as a Verification Specialist in the ASIC industry for more than 20 years. He has worked on several interesting projects ranging from microcontrollers, networking protocols, CPU chipsets, to SoC integration. At Synopsys, Paul works directly with customers and supports them in methodology adoption and coverage methodology, and helps them deploy Synopsys’ Verification IP utilizing best practices to rapidly build effective verification environments.
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