Shift Left with Static & Formal Verification: Catching bugs early for RTL signoff

Date: December 6, 2017 Time: 10 AM PDT

With increasing complexity in chip designs, IP and SoC teams are faced with the challenge of minimizing risk, while still maintaining high levels of productivity.  Poorly coded RTL is a primary concern, as it leads to bugs, longer verification cycles, unpredictable design processes and delayed time to market.

The combination of static and formal technologies enables smarter, faster and deeper lint analysis at RTL for early signoff. These advanced capabilities enable designers to perform a series of even more comprehensive checks, ensuring fewer bugs, a more stable design flow and accelerated verification closure.

In this webinar, we will discuss how SpyGlass® Lint Turbo, VC Formal™ Auto Extracted Properties (AEP) and Formal Coverage Analyzer (FCA) Apps identify RTL issues at their source, pinpoints coding and consistency problems in the RTL descriptions, and helps designers resolve issues quickly before design implementation.  The webinar will also show a tool demo on the easy-to-use Verdi® unified debug capabilities, low noise technology to automatically find RTL bugs, dead code, unreachable FSM states and transitions using advanced static and formal technology.

Kiran Vittal; Product Marketing Director, Verification Group, Synopsys
Kiran Vittal is a product marketing director at Synopsys, with 25 years of experience in EDA and semiconductor design. Prior to joining Synopsys, Kiran held product marketing, field applications and engineering positions at Atrenta and Mentor Graphics. He holds a MBA from Santa Clara University and a Bachelors in Electronics Engineering from India.

Sean O’Donohue; Principal Applications Engineer, Verification Group, Synopsys
Sean O’Donohue is a principal application engineer at Synopsys, responsible for static and formal technologies. Prior to joining Synopsys, Sean was a corporate application engineer at Atrenta and a technical marketing lead at Springsoft.  He holds a Bachelors in Electrical Engineering from Cal Poly Pomona.
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