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Best Practices for FPGA Design Coding, Timing and Congestion Reduction

Date: October 25th, 2017, Time: 10:00 a.m PDT Duration: 60 minutes

The size and complexity of FPGA designs are getting larger with each design and designers are asked to achieve more with less.  One of the big challenges they face is achieving a design that meets timing performance through good coding practices and minimal congestion.  Designers must balance area and timing to achieve good quality of results (QoR) for a cost-effective design. Achieving optimal FPGA timing is not only achieved through the correct creation and utilization of design constraints, but also by the coding style used, which can have an impact on congestion. This is driving a need for a set of tools and methodologies to achieve effective coding and timing closure and alleviate design congestion quickly and easily. Synplify Premier provides designers with automated methods to achieve these goals. This webinar provides tips on design coding, constraint definition, timing closure and how to reduce design congestion for faster turn-around-times.

What you will learn: 
  • How to quickly create and setup your projects
  • Insights on coding style and the impact on timing and congestion
  • Creating and defining the initial design constraints for your FPGA design
  • How to tune the design for the highest performance to achieve timing QoR
  • Tips to lower congestion within the design to accelerate runtimes
Who should attend:

All engineers/managers involved in FPGA design for the industrial, aerospace, communications, automotive, medical or other designs using FPGAs that require high performance.


Paul Owens, Senior Technical Marketing Engineer, Synopsys
Paul Owens is a Senior Technical Marketing Manager within the Verification Group at Synopsys. Paul has worked in Design Automation, CAE, ASIC and FPGA design and verification. He holds a BS in Electrical Engineering from U.C. Berkeley, and an MS in Computer Engineering from Santa Clara University.
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